Solid state imaging device, method of manufacturing the same, and solid state imaging system

ABSTRACT

A solid state imaging device includes a MOS image sensor of a threshold voltage modulation system employed in a video camera, an electronic camera, an image input camera, a scanner, a facsimile, or the like. The solid state imaging device includes a photo diode formed in a second semiconductor layer of opposite conductivity type in a first semiconductor layer of one conductivity type, and a light signal detecting insulated gate field effect transistor formed in a fourth semiconductor layer of the opposite conductivity type in a third semiconductor layer of one conductivity type adjacent to the photo diode. A carrier pocket is provided in the fourth semiconductor layer and a portion of the first semiconductor layer under the second semiconductor layer is thicker than that portion of the third semiconductor layer under the fourth semiconductor layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. Ser. No. 09/715,065 filed Nov.20, 2000, issued as U.S. Pat. No. 6,504,194 Jan. 7, 2003 and claimspriority of Japanese Application No. 11-342587 filed Dec. 1, 1999,Japanese Application No. 11-342588 filed Dec. 1, 1999 and of JapaneseApplication No. 2000-327663 filed Oct. 26, 2000.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a solid state imaging device, a methodof manufacturing the same, and a solid state imaging system and, moreparticularly, a solid state imaging device using a MOS image sensor of athreshold voltage modulation system employed in a video camera, anelectronic camera, an image input camera, a scanner, a facsimile, or thelike, a method of manufacturing the same, and a solid state imagingsystem.

2. Description of the Prior Art

Since a semiconductor image sensor such as a CCD image sensor, a MOSimage sensor, etc. is excellent in mass productivity, such semiconductorimage sensor is applied to most of the image input devices with theprogress of the fine pattern technology.

In particular, the MOS image sensor is reconsidered in recent yearsbecause of its merits that the power consumption is small rather thanthe CCD image sensor and that the sensor element and peripheral circuitelements can be fabricated by the same CMOS technology.

In view of the trend in the times, the applicant of this application hasimproved the MOS image sensor, and then secured the Patent (RegistrationNumber 2935492) by filing the patent application (Patent Application Hei10-186453) in connection with the image sensor device which has thecarrier pocket (high concentration buried layer) under the channelregion.

In the invention of this Patent (Registration Number 2935492), in orderto suppress the injection of the light emitting charges into the surfacedefects of the semiconductor layer and thus reduce the noise, the photodiode has the buried structure for the light emitting charges (in thiscase, holes). More particularly, the n-type impurity region is formed onthe surface layer of the p-type well region. This p-type well region isformed integrally with the p-type base region of the light signaldetecting MOS transistor, and this n-type impurity region is formedintegrally with the n-type drain region. As a result, the configurationcan be formed in which the light emitting charges generated in thep-type well region of the photo diode portion can contribute to thedetection of the light signal.

Meanwhile, in the MOS image sensor, normally the spectral sensitivitycharacteristic, especially the red-color sensitivity is low. Therefore,in order to broaden much more the applications of the MOS image sensorin the future, it is desired to achieve the improvement of the red-colorsensitivity. In addition, it is desired to achieve the improvement ofthe blue-color sensitivity. At the same time, the higher integrationdegree of the solid state imaging device is also desired.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a solid stateimaging device using a MOS image sensor capable of achieving improvementin red-color sensitivity and improvement in blue-color sensitivity whilemaintaining the performance of a light signal detecting MOS transistor,a method of manufacturing the same, and a solid state imaging system.

With reference to FIG. 2A, in order to improve the red-colorsensitivity, it is desired that the n-type epitaxial layer (n-typelayer) 12 on the p-type substrate 11 should be formed thicker than inthe structure of applicants' Patent Registration Number 2935492.However, if the n-type epitaxial layer (n-type layer) 12 is formedthicker, the reset voltage for the initialization to discharge thecarriers must be increased and thus the performance of the light signaldetecting MOS transistor is lowered. In other words, in order to improvethe red-color sensitivity and to maintain/improve the reset efficiency,structures are needed which are incompatible with each other.

In the present invention, as exemplified by the embodiment shown inFIGS. 1 and 2A, in the store period during when the carriers aregenerated by the light in the photo diode 111 having the above structureand then stored in the high concentration buried layer (carrier pocket)25 of opposite conductivity type, the depletion layer can spread from aboundary surface between the one conductivity type impurity region 17and the opposite conductivity type first well region 15 a in the photodiode 111 to the overall first well region 15 a by the applied voltage.Further, the depletion layer can spread from a boundary surface betweenthe opposite conductivity type substrate 11 and the one conductivitytype buried layer 32 in the photo diode 111 to the first semiconductorlayers 12 and 32. Therefore, the light emitting charges generated in thedepleted first well region 15 a and the first semiconductor layers 12and 32 can contribute to the detection of the light signal.

In other words, since the thicknesses of the first semiconductor layers12 and 32 are increased, the thickness of the light receiving region canbe extended effectively with respect to the long wavelength light suchas the red-color. Accordingly, the improvement of the red-colorsensitivity can be achieved.

In contrast, in the sweep period (initialization period) during when thecarriers are swept out from the high concentration buried layer 25 andthe second well region 15 b in the light signal detecting MOS transistor112 portion, the depletion layer can spread from a boundary surfacebetween the one conductivity type channel doped layer 15 c and theopposite conductivity type second well region 15 b into the second wellregion 15 b by the applied voltage, and also the depletion layer canspread from a boundary surface between the opposite conductivity typesixth semiconductor layer 33 and the one conductivity type thirdsemiconductor layer 12 into the third semiconductor layer 12 under thesecond well region 15 b.

As a result, the electric field from the gate electrode 19 can extendmainly to the depleted second well region 15 b and the thirdsemiconductor layer 12 formed under the second well region 15 b.

In the case of the present invention, the thickness of the thirdsemiconductor layer 12 under the second well region 15 b is small andthe opposite conductivity type high concentration sixth semiconductorlayer 33 is formed in the neighborhood of the one conductivity typethird semiconductor layer 12 on the substrate 11 side. Therefore,extension of the depletion layer from the boundary surface between theopposite conductivity type sixth semiconductor layer 33 and the oneconductivity type third semiconductor layer 12 into the sixthsemiconductor layer 33 in the sweep period can be limited, and also thewidth of the depletion layer extending from the boundary surface to thethird semiconductor layer 12 can be reduced. That is, the voltage fromthe gate electrode 19 is mainly applied to the second well region 15 b.

Accordingly, since the abrupt potential change that is fitted to sweepout the carriers is caused in the second well region 15 b and thus thestrong electric field is applied. Therefore, the stored carriers can beswept out effectively from the high concentration buried layer (carrierpocket) 25 and the second well region 15 b by the low reset voltage,whereby the reset efficiency can be improved.

In addition, according to the present invention, since the lowconcentration drain (LDD) structure is employed as the structure of thelight signal detecting MOS transistor 112, the short channel of thelight signal detecting MOS transistor 112 can be achieved and thus thehigher integration degree of the solid state imaging device can beachieved.

Also, the impurity region 117 is formed at the same time when the lowconcentration drain region 117 a is formed. That is, since the impurityconcentration of the impurity region 117 is set to the lowconcentration, the impurity region 117 can be formed at the shallowposition from the surface. Accordingly, the blue-color that has theshort wavelength and attenuates suddenly in the vicinity of the surfacecan be received at the sufficient intensity.

In addition, since the one conductivity type impurity region 17 isformed on the surface layer of the opposite conductivity type first wellregion 15 a serving as the light receiving region, the photo diode 111has the buried structure for the light emitting charges.

Accordingly, since the neutralized state against the trap level of thesurface and the hole generation center can be maintained, the noise andthe dark current due to the charges except the light emitting charge canbe maintained low.

Accordingly, improvement of the blue-color sensitivity can be achievedwhile maintaining the noise and the dark current.

Also, the CMOS circuit for driving the solid state imaging device isformed on the same substrate as the solid state imaging device, and thelow concentration impurity region 17 is formed at the same time when thelow concentration drain region of the MOS transistor constituting theCMOS circuit and having the LDD structure is formed, and in addition thehigh concentration contact layer is formed at the same time when thehigh concentration drain region of the MOS transistor having the LDDstructure is formed.

Accordingly, improvement of the blue sensitivity can be achieved whilemaintaining the noise and the dark current without increasing newmanufacturing steps.

Correspondences between technical terms in the solid state imagingdevice manufacturing method and technical terms in the solid stateimaging device are given as follows. That is, a part of the seventhsemiconductor layers 11 and 31 corresponds to the first base layer, anda part of the seventh semiconductor layers 11 and 31 and the secondburied layer 33 correspond to the second base layer (i.e., the substrate11 and the sixth semiconductor layer). The first buried layer 32corresponds to the buried layer or the fifth semiconductor layer, andthe second buried layer 33 corresponds to the sixth semiconductor layer.The one conductivity type region 12 corresponds to the one conductivitytype well region, and the first buried layer 32 and the one conductivitytype region 12 correspond to the first semiconductor layer (i.e., thefifth semiconductor layer and the one conductivity type well region).The first well region 15 a corresponds to the second semiconductorlayer, and the one conductivity type region 12 corresponds to the oneconductivity type third semiconductor layer (i.e., one conductivity typewell region). The second well region corresponds to the fourthsemiconductor layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view showing a device layout of a unit pixel of a solidstate imaging device according to a first embodiment of the presentinvention;

FIG. 2A is a sectional view showing a device structure of the unit pixelof the solid state imaging device according to a first embodiment of thepresent invention, taken along a I—I line in FIG. 1;

FIG. 2B is a view showing potential behaviors in the situation thatlight emitting holes are stored in a carrier pocket and electrons areinduced in the channel region to generate an inversion region;

FIG. 3 is a sectional view showing a structure of a photo diode in theunit pixel of the solid state imaging device according to the firstembodiment of the present invention, taken along a II—II line in FIG. 1;

FIG. 4 is a sectional view showing a structure of a light signaldetecting MOS transistor in the unit pixel of the solid state imagingdevice according to the first embodiment of the present invention, takenalong a III—III line in FIG. 1;

FIG. 5 is a graph showing an impurity concentration distribution and apotential distribution in the depth direction along a IV—IV line in FIG.2, in the photo diode portion of the solid state imaging deviceaccording to the first embodiment of the present invention;

FIG. 6 is a graph showing an impurity concentration distribution and apotential distribution in the depth direction along a V—V line in FIG. 2crossing the carrier pocket, in the light signal detecting MOStransistor portion of the solid state imaging device according to thefirst embodiment of the present invention;

FIG. 7 is a graph showing a drain current-drain voltage characteristicof the light signal detecting MOS transistor of the solid state imagingdevice according to the first embodiment of the present invention;

FIG. 8 is a view showing an overall circuit configuration of the solidstate imaging device according to the first embodiment of the presentinvention;

FIG. 9 is a timing chart when the solid state imaging device in FIG. 8is operated;

FIG. 10A to FIG. 10R are sectional views showing a method ofmanufacturing the solid state imaging device according to the firstembodiment of the present invention;

FIG. 11 is a plan view showing a device layout of a unit pixel of asolid state imaging device according to a second embodiment of thepresent invention;

FIG. 12 is a sectional view showing a device structure of a unit pixelof the solid state imaging device according to the second embodiment ofthe present invention, taken along a VI—VI line in FIG. 11;

FIG. 13 is a sectional view showing a structure of a photo diode in theunit pixel of the solid state imaging device according to the secondembodiment of the present invention, which is equivalent to a sectionalview taken along a VII—VII line in FIG. 11;

FIG. 14 is a sectional view showing a structure of a light signaldetecting MOS transistor in the unit pixel of the solid state imagingdevice according to the second embodiment of the present invention,which is equivalent to a sectional view taken along a VIII—VIII line inFIG. 11;

FIG. 15 is a graph showing an impurity concentration distribution and apotential distribution in the depth direction along a IX—IX line in FIG.12, in the photo diode portion of the solid state imaging deviceaccording to the second embodiment of the present invention;

FIG. 16A to FIG. 16E are sectional views showing a method ofmanufacturing the solid state imaging device according to the secondembodiment of the present invention; and

FIG. 17 is a sectional view showing a device structure of the unit pixelof the solid state imaging device according to the second embodiment ofthe present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will be explained in detail withreference to the accompanying drawings hereinafter.

(First Embodiment)

FIG. 1 is a plan view showing a device layout of a unit pixel of a solidstate imaging device according to a first embodiment of the presentinvention.

As shown in FIG. 1, a photo diode 111 and a light signal detecting MOStransistor 112 are formed adjacently in a unit pixel 101. They havedifferent well regions, i.e., a first well region (second semiconductorlayer) 15 a and a second well region (fourth semiconductor layer) 15 b,which are coupled in contact mutually, respectively. The first wellregion 15 a of the photo diode 111 portion serves as a part of thecharge generating region which can generate the charges by the lightirradiation. The second well region 15 b of the light signal detectingMOS transistor 112 portion serves as a gate region which can change athreshold voltage of the channel by the potential applied to this region15 b.

An impurity region 17 of the photo diode 111 and a drain region 17 a ofthe light signal detecting MOS transistor 112 are formed integrally suchthat most of the regions overlaps with surface layers of the first wellregion 15 a and the second well region 15 b that communicate each other.The drain region 17 a is formed to surround an outer peripheral portionof a ring-like gate electrode 19. A source region 16 a is formed to besurrounded by an inner periphery of the ring-like gate electrode 19. Inaddition, a carrier pocket (high concentration buried layer) 25, that isa feature of this MOS image sensor, is formed in the second well region15 b under the gate electrode 19 and around the source region 16 a tosurround the source region 16 a.

The drain region 17 a is connected to a drain voltage (VDD) supply line22 via a low resistance contact layer 17 b. The gate electrode 19 isconnected to a vertical scanning signal (VSCAN) supply line 21. Thesource region 16 a is connected to a vertical output line 20 via a lowresistance contact layer 16 b.

Also, an insulating film covers the elements described above. A regionother than a light receiving window 24 of the photo diode 111 islight-shielded by a metal layer (light shielding film) 23 formed on thecovering insulating film.

In the above MOS image sensor, a device operation for detecting thelight signal is carried out repeatedly like sweep period (initializationperiod)-store period-read period-sweep period (initialization period)- .. . .

In the sweep period (initialization period), before the light emittingcharges (light emitting carriers) are stored, the carrier pocket 25 ismade empty by eliminating the light emitting charges which have beenread. In addition, residual charges such as the holes, the electrons,etc., which are trapped at the surface state or neutralize acceptors,donors, etc., are eliminated from the semiconductor prior to the readingof the light signal. A voltage of more than about +5 V, normally about 7to 8 V, is applied to the source region, the drain region, and the gateelectrode.

In the store period, the carriers are generated by the lightirradiation, then drifted in the first well region 15 a and the secondwell region 15 b, and then stored in the carrier pocket 25. A voltage ofalmost +2 to 3 V is applied to the drain region, and also a low voltageby which the MOS transistor 112 can be held at its cut-off state isapplied to the gate electrode.

In the read period, change in the threshold voltage of the light signaldetecting MOS transistor due to the light emitting charges stored in thecarrier pocket is read as change in source potential. In order to makethe MOS transistor 112 operate in its saturation state, a voltage ofalmost +2 to 3 V is applied to the drain region and a voltage of almost+2 to 3 V is applied to the gate electrode.

Next, a device structure of the MOS image sensor according to the firstembodiment of the present invention will be explained with reference toa sectional view hereunder.

FIG. 2A is a sectional view showing a device structure of the solidstate imaging device according to the first embodiment of the presentinvention, which is equivalent to a sectional view taken along a I—Iline in FIG. 1. FIG. 2B is a view showing potential behaviors along asurface of the semiconductor substrate.

FIG. 3 is a sectional view taken along a II—II line in FIG. 1. FIG. 4 isa sectional view taken along a III—III line in FIG. 1.

As shown in FIG. 2A, an epitaxial layer 31 is formed by epitaxiallygrowing p-type silicon, whose impurity concentration is more than 1×10¹⁵cm⁻³ and whose thickness is more than 3 μm, on a p-type siliconsubstrate 11 whose impurity concentration is more than 1×10¹⁸ cm⁻³. Theabove constructs a seventh semiconductor layer of opposite conductivitytype.

A unit pixel consisting of the photo diode 111 and the light signaldetecting MOS transistor 112 is formed on the epitaxial layer 31. Then,a field insulating film 14 and an element isolation layer 13 are formedbetween adjacent unit pixels 101 to isolate the unit pixels 101. Thefield insulating film 14 is formed on a surface of the epitaxial layer31, and an element isolation layer 13 is formed as a p-type highconcentration region to extend over the epitaxial layer 31.

Next, details of the photo diode 111 will be explained with reference toFIG. 2A and FIG. 3 hereunder.

The photo diode 111 consists of an n-type buried layer (one conductivitytype buried layer, first buried layer) 32 buried in the epitaxial layer31 to come into contact with the substrate 11, a low concentrationn-type well layer (one conductivity type region) 12 formed on the n-typeburied layer 32, a p-type first well region 15 a formed on a surfacelayer of the n-type well layer 12, and an n-type impurity region 17formed on the surface layer of the n-type well layer 12 such that itsmost region can overlap with the p-type first well region 15 a.

This photo diode 111 is characterized in that the n-type buried layer 32having the relatively high impurity concentration is provided on theoverall region formed between the substrate 11 and the n-type well layer12 and that the overall n-type layers (first semiconductor layer) 12 and32 under the first well region 15 a are formed thick.

An impurity concentration distribution of this case is shown in FIG. 5.FIG. 5 is a graph showing an impurity concentration distribution and apotential distribution in the depth direction along a IV—IV line in FIG.2, in the center portion of the photo diode 111. An abscissa denotes adepth (μm) from a surface of the semiconductor substrate in a linearscale, and an ordinate on the left side denotes an impurityconcentration (cm⁻³) in a logarithmic scale and an ordinate on the rightside denotes potential (arbitrary unit) in a linear scale.

As shown in the impurity concentration distribution of FIG. 5, athickness of the n-type buried layer 32 is almost 1 μm and a thicknessof the n-type layer 12 under the first well region 15 a is almost 0.5μm. Thus, the thickness of the n-type layers 12 and 32 under the firstwell region 15 a are almost 1.5 μm.

The above thickness of the n-type layers 12 and 32 under the first wellregion 15 a, the impurity concentration distribution, its peak value,and a depth of a peak position are selected to be optimal when a voltageapplied in a store period is about 2 to 3 V. The thickness of the n-typelayer 12 and the n-type buried layer 32 under the first well region 15a, the impurity concentration distribution, the peak value, and thedepth of the peak position are set such that a depletion layer can bespread sufficiently into the overall n-type layers 12 and 32 by theapplied voltage mainly in the store period of carriers and the lightreceiving sensitivity of the red light can be enhanced sufficiently.Accordingly, these values may be changed appropriately depending upon athickness of the first well region 15 a, an impurity concentrationdistribution, its peak value, and a depth of a peak position, anattenuation characteristic of the red-color in the semiconductor, or avalue of the voltage applied in the store period of the carriers.

In the photo diode 111 having the above structure, the n-type impurityregion 17 is connected to the drain voltage supply line 22 in the abovestore period and biased to a positive potential. At this time, thedepletion layer can spread from a boundary surface between the impurityregion 17 and the first well region 15 a to the overall first wellregion 15 a to reach the n-type layer 12. In contrast, the depletionlayer can spread from a boundary surface between the substrate 11 andthe n-type buried layer 32 to all the n-type buried layer 32 and theoverlying n-type well layer 12 to reach the first well region 15 a.

The potential distribution at this time is shown in FIG. 5. Since thephoto diode 111 portion has the above impurity concentrationdistribution, the first well region 15 a and the n-type layers 12 and 32have the potential distribution in which the potential is graduallyreduced from the substrate 11 side to the surface side. Therefore, theholes generated by the light in the first well region 15 a and then-type layers 12 and 32 do not flow to the substrate 11 side, but stayin the first well region 15 a and the n-type layers 12 and 32. Since thefirst well region 15 a and the n-type layers 12 and 32 are connected tothe gate region 15 b of the light signal detecting MOS transistor 112,these holes generated by the light can be effectively utilized as thecharges to modulate the threshold voltage of the light signal detectingMOS transistor 112. In other words, all the first well region 15 a andthe n-type layers 12 and 32 can act as the carrier generating region bythe light.

In this manner, because the n-type buried layer 32 is provided, a totalthickness of the carrier generating region of the photo diode 111becomes thick. Accordingly, when the light is irradiated to the photodiode 111, such carrier generating region can act as the light receivingportion that has the good sensitivity to the light having a longwavelength, like the red color, which comes up to a deep inside of thelight receiving portion.

Also, the photo diode 111 has the buried structure for the holesgenerated by the light in the meaning that the carrier generating regionby the light is arranged under the impurity region 17 in the above photodiode 111. Therefore, the noise reduction can be achieved without theinfluence of the surface of the semiconductor layer which has manyinterface trap levels.

Next, details of the light signal detecting MOS transistor (nMOS) 112will be explained with reference to FIGS. 2A and 2B and FIG. 4hereunder.

The MOS transistor 112 of the first embodiment has a structure that then⁺-type drain region 17 a surrounds an outer periphery of the ring-likegate electrode 19. The n⁺-type drain region 17 a is formed integrallywith n⁺-type impurity region 17. Also, the n⁺-type source region 16 a isformed to be surrounded by the ring-like gate electrode 19. In otherwords, the gate electrode 19 is formed on the second well region 15 bbetween the drain region 17 a and the source region 16 a via a gateinsulating film 18. A surface layer of the second well region 15 bformed under the gate electrode 19 acts as the channel region.

In addition, in order to hold the channel region at its inverted stateor its depletion state in the normal operation voltage, a channel dopedlayer 15 c is formed by introducing the n-type impurity having anappropriate concentration into the channel region.

The p⁺-type carrier pocket (high concentration buried layer) 25 isformed in a partial area over the channel length direction in the secondwell region 15 b under the channel region, i.e., in a peripheral area ofthe source region 16 a to surround the source region 16 a. This p⁺-typecarrier pocket 25 can be formed by the ion implantation method, forexample. The carrier pocket 25 is formed in the second well region 15 bwhich is positioned deeper than the channel region. It is desired thatthe carrier pocket 25 should be formed not to overlap with the channelregion.

Since the potential against the light emitting holes out of the lightemitting charges is lowered in the above p⁺-type carrier pocket 25, thelight emitting holes can be collected into the carrier pocket 25 when avoltage higher than the gate voltage is applied to the drain region 17a.

The potential in the state that the light emitting holes are stored inthe carrier pocket 25 and the electrons are induced in the channelregion to thus form the inversion region is shown in FIG. 2B. Thethreshold voltage of the light signal detecting MOS transistor 112 ischanged by the stored charges. Accordingly, detection of the lightsignal can be performed by detecting the change in the thresholdvoltage.

FIG. 6 is a graph showing an impurity concentration distribution and apotential distribution in the depth direction along a V—V line in FIG. 2crossing the carrier pocket 25 portion in the light signal detecting MOStransistor 112.

An abscissa denotes the depth (μm) from the surface of the semiconductorsubstrate in a linear scale, and an ordinate on the left side denotesthe impurity concentration (cm⁻³) in a logarithmic scale and an ordinateon the right side denotes the potential (arbitrary unit) in a linearscale.

As indicated by the impurity concentration distribution of FIG. 6, it ischaracterized that a p-type buried layer (second buried layer) 33 ofhigh impurity concentration is provided between the substrate 11 and then-type well layer 12. In other words, an n-type layer (thirdsemiconductor layer) under the second well region 15 b coincides withthe n-type well layer 12, and thus a boundary between the n-type layerand the p-type buried layer 33 is positioned at a depth of about 0.8 μmfrom the surface. A thickness of the n-type layer under the second wellregion 15 b is about 0.4 μm, which is thinner than the about 1.5 μmthickness of the n-type layers (first semiconductor layer) 12 and 32below the first well region 15 a in the photo diode 111 portion.

Also, a peak position of the impurity concentration of the p-type buriedlayer 33 is positioned at a depth of about 1.1 μm, and the impurityconcentration at the peak position is almost 5×10¹⁶ cm⁻³.

The thicknesses of the n-type layer 12 and the p-type buried layer 33under the second well region 15 b, the impurity concentrationdistribution, the peak value, and the depth of the peak position are setto be optimal when a reset voltage is set to 7 to 8 V. The impuritydistribution and the depth of the n-type layer 12 and the p-type buriedlayer 33 are set such that the depletion layer, mainly in the carriersweep period (initialization period), can spread into the second wellregion 15 b rather than the p-type buried layer 33 to concentrate theelectric field in the second well region 15 b. Accordingly, these valuesmay be changed appropriately depending upon a thickness of the secondwell region 15 b, an impurity concentration distribution in the region15 b, its peak value, and a depth of a peak position, or a value of thevoltage (reset voltage) applied in the carrier sweep period(initialization period).

In this case, the carrier pocket 25 is formed at a depth of about 0.2μm, and the peak value of the impurity concentration is set to about1×10¹⁷ cm⁻³. The thickness of the carrier pocket 25, a peak value of itsimpurity concentration, and a depth of its peak position are set suchthat the potential to store sufficiently the carriers in the carrierpocket can be obtained in the store period and the read period mainlyand that the carrier storing state in the carrier pocket 25 can have anenough effect on the channel region in the read period. Accordingly,these values may be changed appropriately depending upon a state of theimpurity concentration distribution of the first well region 15 aserving as the background of the carrier pocket 25, an impurityconcentration of the channel doped layer, the applied voltage in thestore period, the applied voltage in the read period, etc.

By the way, in the above carrier sweep period, the carriers remained inthe second well region 15 b are swept to the substrate 11 side by theelectric field which is generated by applying the high voltage to thegate electrode 19, the source region 16 a, and the drain region 17 a. Inthis case, the depletion layer spreads from a boundary surface betweenthe channel doped layer 15 c in the channel region and the second wellregion 15 b into the second well region 15 b by the applied voltage, andalso the depletion layer spreads from a boundary surface between thep-type buried layer 33 and the n-type well layer 12 into the n-type welllayer 12 under the second well region 15 b.

As a result, the electric field generated by the voltage applied to thegate electrode 19 extends mainly over the second well region 15 b andthe n-type well layer 12 formed under the second well region 15 b.

In the case of the present invention, the n-type well layer 12 under thesecond well region 15 b is small in thickness and the high concentrationp-type buried layer 33 is formed in the neighborhood of the n-type welllayer 12 on the substrate 11 side. For this reason, the depletion layerthat spreads from a boundary surface between the p-type buried layer 33and the n-type well layer 12 into the n-type well layer 12 in the seepperiod becomes small in thickness.

More particularly, as indicated by the potential distribution of FIG. 6,the voltage supplied from the gate electrode 19 is applied mainly to thesecond well region 15 b. In other words, since the abrupt potentialchange is caused in the second well region 15 b and thus the strongelectric field that can sweep out the holes to the substrate 11 side ismainly applied to the second well region 15 b, the carriers stored inthe carrier pocket 25 and the second well region 15 b can be swept bythe low reset voltage without fail, whereby a reset efficiency can beimproved.

Next, an overall configuration of the MOS image sensor using the unitpixel having the above structure will be explained with reference toFIG. 8 hereunder. FIG. 8 shows a circuit configuration of the MOS imagesensor according to the first embodiment of the present invention.

As shown in FIG. 8, this MOS image sensor has a two-dimensional arraysensor configuration in which the unit pixels having the above structureare aligned in the column direction and the row direction in a matrixfashion.

Also, a vertical scanning signal (VSCAN) drive scanning circuit 102 anda drain voltage (VDD) drive scanning circuit 103 are arranged on theright and left sides to put the pixel region between them.

Vertical scanning signal supply lines 21 a, 21 b are extended from thevertical scanning signal drive scanning circuit 102 one by one everyrow. The vertical scanning signal supply lines 21 a, 21 b are connectedto the gates of the MOS transistors 112 in all unit pixels 101 along therow direction.

Also, drain voltage supply lines (VDD supply lines) 22 a, 22 b areextended one by one every row from the drain voltage drive scanningcircuit 103. The every drain voltage supply line 22 a, 22 b is connectedto the drains of the light signal detecting MOS transistors 112 in allunit pixels 101 along the row direction.

Also, different vertical output lines 20 a, 20 b are provided everycolumn. The vertical output lines 20 a, 20 b are connected to sources ofthe MOS transistors 112 in all unit pixels 101 aligned along the columndirection respectively.

In addition, MOS transistors 105 a, 105 b acting as different switchesare provided every column. The vertical output lines 20 a, 20 b areconnected to drains (light detecting signal input terminals) 28 a, 29 aof the MOS transistors 105 a, 105 b one by one. Gates (horizontalscanning signal input terminals) 28 b, 29 b of the switches 105 a, 105 bare connected to a horizontal scanning signal (HSLAN) drive scanningcircuit 104.

Also, sources (light detecting signal output terminals) 28 c, 29 c ofthe switches 105 a, 105 b are connected to a video signal outputterminal 107 via a common constant current source (load circuit) 106. Inother words, the source of the MOS transistor 112 in the every unitpixel 101 is connected to the constant current source 106 to form asource follower circuit of the every unit pixel. Therefore, a potentialdifference between the gate and the source of the MOS transistor 112 anda potential difference between the bulk and the source are decided bythe constant current source 106 connected thereto.

A video signal (Vout) that is in proportion to an incident amount of thelight can be read by driving the MOS transistor 112 of the unit pixelsequentially by the vertical scanning signal (VSCAN) and the horizontalscanning signal (HSCAN).

FIG. 9 shows a timing chart of input/output signals to operate the MOSimage sensor according to the present invention. The case is appliedwhere the p-type well regions 15 a, 15 b are used and the light signaldetecting transistor 112 is composed of nMOS.

As described above, the device operation is repeated such as the sweepperiod (initialization period)-the store period-the read period-thesweep period (initialization period)- . . . .

Next, a series of continuous light detecting operations of the solidstate imaging device will be explained simply in compliance with FIG. 8and FIG. 9.

First, the charges remaining in the carrier pocket 25 and the wellregions 15 a, 15 b are exhausted by the initializing operation. Moreparticularly, a high positive voltage of about 6 V is supplied to thedrain of the light signal detecting MOS transistor 112 via the VDDsupply lines 22 a, 22 b and supplied to the gate of the light signaldetecting MOS transistor 112 via the VSCAN supply lines 21 a, 21 b. Atthis time, since the n-type well layer 12 under the second well region15 b is small in thickness and the high concentration p-type buriedlayer 33 comes into contact with the n-type well layer 12 on thesubstrate 11 side, the voltage applied to the gate electrode 19 isapplied merely to the second well region 15 b and its very close region.In other words, the abrupt change of the potential is caused in thesecond well region 15 b, and thus the strong electric field for sweepingout the holes to the substrate 11 side is applied mainly to the secondwell region 15 b. Therefore, the carriers can be swept out by the lowreset voltage without fail, whereby the improvement of the resetefficiency can be achieved.

Then, the low gate voltage is applied to the gate electrode 19 of thelight signal detecting MOS transistor 112, and the voltage (VDD) ofabout 2 to 3 V necessary for the transistor operation is applied to thedrain region 17 a. At this time, the first well region 15 a, the n-typewell region 12, and the n-type buried layer 32 are depleted and also thesecond well region 15 b is depleted. Then, the electric field isgenerated to direct from the drain region 17 a to the source region 16a.

Then, the light is irradiated onto the photo diode 111. At this time,the carrier generating region in the photo diode 111 portion is totallythick. Therefore, electron-hole pairs (light emitting charges) can begenerated effectively with respect to the long wavelength light such asthe red-color light which can reach the deep inside of the lightreceiving portion.

The light emitting holes out of the light emitting charges are injectedinto the gate region of the light signal detecting MOS transistor 112 bythe above electric field and then stored in the carrier pocket 25.Accordingly, the width of the depletion layer that is extended from thechannel region to the underlying gate region 15 b is limited and alsothe potential in the neighborhood of the source region 16 a ismodulated, whereby the threshold voltage of the light signal detectingMOS transistor 112 is changed.

Then, the gate voltage of about 2 to 3 V to operate the MOS transistor112 in its saturation state is applied to the gate electrode 19, and thevoltage VDD of about 2 to 3 V to operate the MOS transistor 112 isapplied to the drain region 17 a. Accordingly, a low electric fieldinversion region is formed in a part of the channel region over thecarrier pocket 25 and also a high electric field region is formed inremaining portion of the channel region. At this time, as shown in FIG.7, a drain current-drain voltage characteristic of the light signaldetecting MOS transistor 112 exhibits the saturation characteristic.

Then, the constant current source 106 is connected to the source region16 of the MOS transistor 112 to flow a constant current. Accordingly,since the MOS transistor 112 forms the source follower circuit, thesource potential is changed to follow up the change of threshold voltageof the MOS transistor by the light emitting holes and thus change of theoutput voltage is brought about.

In this manner, the video signal (Vout) that is in proportion to anirradiation amount of the light can be picked up.

As described above, according to the first embodiment of the presentinvention, an ideal photoelectric conversion mechanism can beaccomplished which does not interact with noise sources on thesemiconductor surface and in the channel region when the light emittingholes are drifted in a series of processes of the sweeping operation(initialization)—the storing operation—the reading operation.

Also, since the transistor can be operated in its saturation state, asshown in FIG. 7, by the charge accumulation into the carrier pocket 25and also the source follower circuit is formed, the change of thethreshold voltage due to the light emitting charges can be detected asthe change in the source potential. As a result, the photoelectricconversion can be achieved with good linearity.

Next, a method of manufacturing the solid state imaging device havingthe above configuration will be explained with reference to FIG. 10A toFIG. 10R hereunder.

In this case, an actual circuit configuration is complicated and isdifferent from planar arrangement of the elements described in thefollowing. In FIG. 10A to FIG. 10R, for convenience of explanation ofthe manufacturing method, major elements are schematically shown toillustrate how to form different device structures in a series ofmanufacturing steps. The major elements are picked up out of allelements employed in this circuit and have a different structure eachother. As types of the selected elements, p-CMOS (p-channel MOS ofComplementary Metal Oxide Semiconductor) as a peripheral circuit device,n-CMOS (n-channel MOS of CMOS), enhancement n-MOS, depletion n-MOS, andVMIS as the optical sensor are illustrated from the left side offigures.

First, as shown in FIG. 10A, an epitaxial layer 31 of about 3 μmthickness is formed by epitaxial-growing p-type silicon whose impurityconcentration is about 1×10¹⁵ cm⁻³ on a p-type silicon substrate 11whose impurity concentration is about 4×10¹⁸ cm⁻³. The substrate 11constitutes an entire part of a first base layer and a part of a secondbase layer, and the epitaxial layer 31 constitutes a part of the secondbase layer.

Then, as shown in FIG. 10B, a field insulating film 14 is formed in theelement isolation region by LOCOS (LOCal Oxidation of Silicon). Then, apad insulating film 51 is formed in the element forming region that issurrounded by the element isolation region.

Then, a resist mask 52 that has opening portions 53 a, 53 b in theelement isolation region between the enhancement n-MOS and the depletionn-MOS and the element isolation region between the depletion n-MOS andthe VMIS respectively and has an opening portion 53 c to spread over then-CMOS forming region is formed. In turn, the p-type impurity ision-implanted via the opening portions 53 a, 53 b, 53 c of the resistmask 52 and the field insulating film 14. Therefore, p-type elementisolation layers 13 are formed in the epitaxial layer 31 under the fieldinsulating film 14 between the enhancement n-MOS and the depletion n-MOSand between the depletion n-MOS and the VMIS to reach the substrate 11,and also a p-type well layer 54 is formed in the epitaxial layer 31spreading over the n-CMOS forming region to reach the substrate 11.

Then, as shown in FIG. 10C, a resist mask (first mask) 55 with anopening portion 56 in the photo diode 111 forming region in the VMISforming region is formed. In turn, P31+ as the n-type impurity ision-implanted deeply through the opening portion 56 of the resist mask55 via the pad insulating film 51, and then B11+ as the p-type impurityis ion-implanted two times shallowly through the same opening portion56. Therefore, as shown in FIG. 5, an n-type buried layer (first buriedlayer) 32 with a peak position of about 1.5 μm and a peak impurityconcentration of about 1×10¹⁷ cm⁻³ is formed to come into contact withthe substrate 11, and a p-type well layer 15 a with a peak position ofabout 0.3 μm and a peak impurity concentration of about 6×10¹⁶ cm⁻³ andwith another peak position of about 0.55 μm and another peak impurityconcentration of about 2×10¹⁶ cm⁻³ is formed over the n-type buriedlayer 32. This p-type well layer 15 a acts as the first well region(second semiconductor layer) having the width being substantially sameas the n-type buried layer 32. This n-type buried layer 32 constitutes apart of the first semiconductor layer.

Then, as shown in FIG. 10D, a resist mask 57 that has an opening portion58 to extend over an entire area of the VMIS forming region is formed.In turn, the n-type impurity is ion-implanted through the openingportion 58 of the resist mask 57. Therefore, an n-type well layer(opposite conductivity type region) 12 with a peak position of about0.55 μm and a peak impurity concentration of about 3×10¹⁶ cm⁻³ is formedto contain the overall first well region 15 a and to reach the n-typeburied layer 32 at its bottom end. This n-type well layer 12 constitutesa part of the first semiconductor layer and the overall thirdsemiconductor layer.

Then, after the step shown in FIG. 10D, a gate insulating film may alsobe formed by removing the pad insulating film 51 and then re-oxidizingthe surface of the semiconductor substrate. In FIG. 10D, the padinsulating film 51 and the gate insulating film being formed by there-oxidation are denoted together by the same reference number 51. Inthis case, preferably the gate insulating film is set to the thicknessof less than 60 nm. This is because, if the thickness is set thickerthan this value, it is difficult to get the sharp impurity concentrationdistribution when the high concentration buried layer 25 is formed bythe ion implantation.

Then, as shown in FIG. 10E, a resist mask (second mask) 60 that has anopening portion 61 a in the forming region of the light signal detectingMOS transistor 112 in the VMIS forming region and has an opening portion61 b to extend over the overall depletion n-MOS forming region isformed. In turn, B11+ as the p-type impurity is ion-implanted deeplythrough the opening portions 61 a and 61 b of the resist mask 60, andthen B11+ as the p-type impurity is ion-implanted shallowly through thesame opening portions 61 a and 61 b. In addition, As+ as the n-typeimpurity is ion-implanted shallowly through the same opening portions 61a and 61 b.

Accordingly, a p-type buried layer 62, a p-type well layer 63, and achannel doped layer 64 are formed in the depletion n-MOS forming region.In contrast, as shown in FIG. 6, a p-type buried layer (second buriedlayer) 33 with a peak position of about 1.2 μm and a peak impurityconcentration of about 5×10¹⁶ cm⁻³, a second well region 15 b with apeak position of about 0.1 μm and a peak impurity concentration of about1.2×10¹⁷ cm⁻³, and an n-type channel doped layer 15 c with a surfaceconcentration of about 2×10¹⁷ cm⁻³ are formed in the VMIS formingregion. The p-type buried layer 33 constitutes a part of the second baselayer.

Then, as shown in FIG. 10F, a resist mask 65 that has an opening portion66 over all the p-CMOS forming region, the n-CMOS forming region, andthe enhancement n-MOS forming region is formed. In turn, the p-typeimpurity is shallowly ion-implanted via the opening portion 66 of theresist mask 65. Therefore, the p-type channel doped layers 67 a to 67 care formed.

Then, as shown in FIG. 10G, a resist mask 68 that has an opening portion69 in the p-CMOS forming region is formed. Then, an n-type well layer 70is formed by ion-implanting the n-type impurity via the opening portion69 of the resist mask 68.

Then, as shown in FIG. 10H, a resist mask (third mask) 71 that has anopening portion 72 in the region serving as the carrier pocket (highconcentration buried layer) 25 of the light signal detecting MOStransistor in the VMIS forming region is formed. In turn, B11+ as thep-type impurity is ion-implanted via the opening portion 72 of theresist mask 71. Therefore, as shown in FIG. 6, a p⁺-type highconcentration buried layer 25 with a peak position of about 0.2 μm and apeak impurity concentration of about 1×10¹⁷ cm⁻³ is formed in the secondwell region 15 b under the channel doped layer 15 c.

Then, as shown in FIG. 10I, a resist mask 73 that has an opening portion74 to extend over all the p-CMOS forming region, the n-CMOS formingregion, the enhancement n-MOS forming region, and the depletion nMOSforming region is formed. In turn, the gate oxide film 51 is removed viathe opening portion 74 of the resist mask 73, and the original gateoxide film 51 is left in the VMIS forming region.

Then, as shown in FIG. 10J, after the resist mask 73 is removed, thesurface of the semiconductor substrate is thermally oxidized. Therefore,thin gate oxide films 75 a to 75 d are formed in the p-CMOS formingregion, the n-CMOS forming region, the enhancement n-MOS forming region,and the depletion n-MOS forming region, and also a thick gate insulatingfilm 18 is formed on the surface of the VMIS forming region since athickness of a new oxide film is further added to the thickness of theoxide film being left in the preceding step. Thus, the gate capacity canbe reduced by increasing the thickness of the gate insulating film 18 inthe VMIS forming region, so that the detecting sensitivity of the lightemitting charges stored in the high concentration buried layer, in turn,the light signal detecting sensitivity can be improved.

Then, as shown in FIG. 10K, a polysilicon film 76 is formed on anoverall surface.

Then, as shown in FIG. 10L, gate electrodes 76 a to 76 e, 19 are formedin respective MOS forming regions by patterning the polysilicon film 76.

Then, as shown in FIG. 10M, a resist mask 77 that has an opening portion78 to extend over the entire pCMOS forming region is formed. Then, thep-type impurity is ion-implanted via the opening portion 78 of theresist mask 77 by using the gate electrode 76 e as a mask. Therefore,source/drain regions 79 a and 79 b are formed in the n-type well layer70 on both sides of the gate electrode 76 e.

Then, as shown in FIG. 10N, a resist mask 80 that has an opening portion81 to extend over all the n-CMOS forming region, the enhancement n-MOSforming region, the depletion n-MOS forming region, and the VMIS formingregion is formed. Then, the n-type impurity is ion-implanted via theopening portion 81 of the resist mask 80 by using the gate electrodes 76b to 76 d, 19 as a mask. Therefore, source/drain regions 82 a and 82 b,82 c and 82 d, 82 e and 82 f, 16 a and 17 a are formed on both sides ofthe gate electrodes 76 b to 76 d, 19 in respective forming regions.

Then, as shown in FIG. 10O, the resist mask 80 is removed and then aninsulating film is formed by the CVD (Chemical Vapor Deposition) method,etc. In turn, sidewalls 83 are formed on side surfaces of the gateelectrodes 76 a to 76 e, 19 by the anisotropic etching.

Then, as shown in FIG. 10P, a resist mask 84 that has an opening portion85 in the p-CMOS forming region is formed. In turn, the p-type impurityis ion-implanted via the opening portion 85 of the resist mask 84 byusing the gate electrode 76 e and the sidewalls 79 as a mask. Therefore,contact layers 86 a and 86 b are formed in the source/drain regions 79 aand 79 b respectively.

Then, as shown in FIG. 10Q, a resist mask 87 that has an opening portion88 to extend over all the n-CMOS forming region, the enhancement n-MOSforming region, the depletion n-MOS forming region and has an openingportion 88 in the light signal detecting MOS transistor 112 portion andthe photo diode 111 portion in the VMIS forming region is formed.Thereafter, the n-type impurity is ion-implanted via the opening portion88 of the resist mask 87. Therefore, contact layers 89 a and 89 b, 89 cand 89 d, 89 e and 89 f, 16 b and 17 b are formed in the source/drainregions 82 a and 82 b, 82 c and 82 d, 82 e and 82 f, 16 a and 17 a inrespective forming regions.

Then, as shown in FIG. 10R, after the resist mask 87 is removed, a firstlayer interlayer insulating film 90 is formed. Then, underlyingsource/drain electrodes or wiring layers 91 a and 91 b, 91 c and 91 d,91 e and 91 f, 91 g and 91 h, 20 and 22 which are connected to thesource/drain regions 82 a and 82 b, 82 c and 82 d, 82 e and 82 f, 79 aand 79 b, 16 a and 17 a in respective MOS forming regions, and a gatewiring layer 21 which are connected to the gate electrode 19 in the VMISforming region are formed on the first layer interlayer insulating film90.

In turn, after an interlayer insulating film 92 of a second layer isformed, overlying source/drain electrodes or wiring layers 91 a and 91b, 91 c and 91 d, 91 e and 91 f, 91 g and 91 h, 20 which are connectedto the underlying source/drain electrodes or wiring layers 91 a and 91b, 91 c and 91 d, 91 e and 91 f, 91 g and 91 h, 20 in respective MOSforming regions are formed on the second layer interlayer insulatingfilm 92.

In turn, after an interlayer insulating film 93 of a third layer isformed, a light shielding film 23 that has an opening portion (lightreceiving window) 24 in the photo diode 111 portion is formed on theinterlayer insulating film 93. Then, a cover insulating film 94 to coverthe overall surface of the device is formed, whereby the solid stateimaging device can be completed.

As described above, according to the first embodiment of the presentinvention, since the unit pixel 101 consists of the photo diode 111 andthe MOS transistor 112, the pixel portion can be fabricated by using theCMOS technology. Therefore, all the above pixel portion and theperipheral circuits such as the drive scanning circuits 102 to 104, theconstant current source 106, etc. are fabricated on the samesemiconductor substrate.

As a result, simplification of the manufacturing steps can be achievedand also size reduction of the solid state imaging device can beachieved by the integration of the circuit parts.

With the above, although the present invention is explained in detailbased on the first embodiment, the scope of the present invention is notlimited to the examples described particularly in the first embodiment.Thus, variation of the above first embodiment may be contained in thescope of the present invention without departing the gist of the presentinvention.

For example, the first well region 15 a and the second well region 15 bare formed separately, but they may be formed integrally at a time.

Also, the p-type epitaxial layer 31 is formed on the p-type substrate11, but the n-type epitaxial layer may be formed on the p-type substrate11. In this case, it is similar to the above embodiment that the n-typelayer (first semiconductor layer) under the first well region 15 a isformed thick but the n-type layer (third semiconductor layer) under thesecond well region 15 b is formed thin.

In addition, although the p-type substrate 11 is used, the n-typesubstrate may be used. In this case, the light emitting carriers to bestored in the carrier pocket 25 are the electrons among the lightemitting holes and the electrons. Thus, in order to achieve the similaradvantages of the above embodiment, the conductivity type of respectivelayers and respective regions explained in the first embodiment shouldbe inversed.

Further, the impurity concentration and the thickness of the n-typeburied layer (first buried layer) 32 may be set to a concentration and athickness such that the depletion layer can spread from a boundarysurface between the substrate 11 and the n-type buried layer 32 to theoverall n-type buried layer 32 by the voltage applied between theimpurity region 17 and the substrate 11 in the store period.

Furthermore, the impurity concentration and the thickness of the p-typeburied layer (second buried layer) 33 may be set to a concentration anda thickness such that, by the voltage applied between the gate electrode19 and the substrate 11 in the carrier sweep period, the depletion layercan spread mainly to the n-type well layer 12 from a boundary surfacebetween the p-type buried layer 33 and the n-type well layer 12 but suchdepletion layer scarcely spreads to the p-type buried layer therefrom.

The sequence of steps shown in the above embodiment of the solid stateimaging device is merely a representative example. The sequence of stepsshown in the above embodiment may be changed appropriately if a devicestructure equivalent to the desired device structure obtained by theabove manufacturing method can be derived.

As described above, according to the present invention, the photo diodeand the light signal detecting MOS transistor are formed adjacently, andthe thickness of the first semiconductor layer under the first wellregion (second semiconductor layer) of the photo diode portion is largerthan that of the third semiconductor layer under the second well region(fourth semiconductor layer) of the light signal detecting MOStransistor portion.

In the photo diode portion, since the first semiconductor layer underthe first well region is increased in thickness, the light receivingregion can be extended effectively with respect to the long wavelengthlight such as the red-color in the store period of the carriers.Accordingly, the improvement of the red-color sensitivity can beachieved.

In contrast, in the light signal detecting MOS transistor portion, sincethe third semiconductor layer under the second well region is reduced inthickness and the high concentration second buried layer is formedadjacent to the third semiconductor layer on the substrate side, thevoltage supplied from the gate electrode is not so applied to the secondsemiconductor layer in the carrier sweep period but applied mainly tothe second well region. As a result, since the strong electric field isapplied to the second well region, the stored carriers can be swepteffectively out from the high concentration buried layer (carrierpocket) and the second well region by the low reset voltage, and thusthe improvement of the reset efficiency can be the embodiment can beachieved.

(Second Embodiment)

Next, a planar layout and a sectional structure of a device in a unitpixel of a MOS image sensor according to a second embodiment of thepresent invention.

The planar layout of the device in the unit pixel is shown in FIG. 11.In this case, features reside in an impurity region 117, drain regions117 a, 117 b, and source regions 116 a, 116 b. However, since the planararrangement is similar to FIG. 1 in the first embodiment, itsexplanation will be omitted.

Next, a device structure of the MOS image sensor according to the secondembodiment of the present invention will be explained with reference tothe sectional views of FIG. 12, FIG. 13, and FIG. 14 hereunder.

FIG. 12 is a sectional view showing the device structure of the MOSimage sensor according to the second embodiment, taken along a VI—VIline in FIG. 11. Since the potential behaviors along the surface of thesemiconductor substrate are similar to those in FIG. 2B, such potentialbehaviors will be referred to.

FIG. 13 is a sectional view taken along a VII13 VII line in FIG. 11, andFIG. 14 is a sectional view taken along a VIII—VIII line in FIG. 11.

A difference from the first embodiment resides in that the light signaldetecting MOS transistor 112 has a low concentration drain structure(LDD structure).

Also, another difference resides in that the impurity region 117 of thephoto diode 111 that has the substantially same impurity concentrationas the low concentration drain region 117 a is formed by extending thelow concentration drain region 117 a of the light signal detecting MOStransistor 112.

That is, the impurity region 117 and the low concentration drain region117 a are formed integrally with each other such that most of them canoverlap with the surface layer of the first well region 15 a and thesecond well region 15 b that are connected mutually.

Also, the high concentration drain region, i.e., the low resistancecontact layer 117 b is formed in outer peripheral portions of theimpurity region 117 and the low concentration drain region 117 a suchthat it can be connected to the low concentration drain region 117 awhile avoiding the light receiving portion. The impurity region 117 andthe low concentration drain region 117 a are formed shallower in depththan the contact layer 117 b.

Also, an n-type low concentration source region 116 a in the peripheralportion and a high concentration source region 116 b in the centerportion as the contact layer connected to the source region 116 a areformed to be surrounded by the ring-like gate electrode 19.

In other words, the surface layer of the second well region 15 b underthe gate electrode 19 acts as the channel region. Like the firstembodiment, in order to keep the channel region at its inverted state orits depletion state in the normal operation voltage, the channel dopedlayer 15 c is formed by introducing the n-type impurity into the channelregion at the appropriate concentration.

In FIGS. 11 to 14, elements indicated by the same reference as those inFIG. 1, FIG. 2A, FIG. 3 and FIG. 4 denote the same elements as those inFIG. 1, FIG. 2A, FIG. 3 and FIG. 4.

An impurity concentration distribution of the photo diode 111 portion isshown in FIG. 15. FIG. 15 is a graph showing an impurity concentrationdistribution and a potential distribution of a center portion of thephoto diode 111 in the depth direction along a IX—IX line in FIG. 12. Anabscissa denotes the depth (μm) from the surface of the semiconductorsubstrate in a linear scale, and an ordinate on the left side denotesthe impurity concentration (cm⁻³) in a logarithmic scale and an ordinateon the right side denotes the potential (arbitrary unit) in a linearscale.

As indicated by the impurity concentration distribution of FIG. 15, athickness of the impurity region 117 is about 200 nm from the surface, apeak position of the impurity concentration of the impurity region 117is at a depth of less than 50 nm, and the impurity concentration at thepeak position is almost 3×10¹⁸ cm⁻³.

A thickness of the n-type buried layer 32 is about 1 μm and a thicknessof the n-type layer 12 under the first well region 15 a is about 0.5 μm.Thus, a total thickness over the n-type layers 12 and 32 under the firstwell region 15 a of the photo diode 111 is about 1.5 μm. A peak positionof the impurity concentration of the above impurity region 117 and animpurity concentration at the peak position may be changedappropriately.

In the photo diode 111 having the above structure, since the impurityregion 117 is formed shallower in depth by setting the impurityconcentration of the impurity region 117 to the low concentration, evena blue-color light that has the short wavelength and attenuates abruptlyin the neighborhood of the surface can be received at the sufficientintensity.

Since the low concentration drain (LDD) structure is employed as thestructure of the light signal detecting MOS transistor 112, the shortchannel of the light signal detecting MOS transistor 112 can be achievedand thus the higher integration degree of the solid state imaging devicecan be achieved.

In FIG. 12, the impurity concentration distribution along an X—X linepassing through the carrier pocket 25 of the light signal detecting MOStransistor 112 portion is substantially similar to FIG. 6, and itsexplanation will be omitted.

In addition, since a solid state imaging system containing the abovesolid state imaging device has the structure similar to the firstembodiment and can be driven similarly in the first embodiment, itsexplanation will be omitted.

Next, a method of manufacturing the solid state imaging device havingthe above structure will be explained with reference to FIG. 16A to FIG.16E hereunder.

FIG. 16A is a sectional view showing a state that the gate electrode 19is formed. In FIG. 16A, a reference 11 denotes the p-type siliconsubstrate with an impurity concentration of about 4×10¹⁸ cm⁻³. Anepitaxial layer of about 3 μm thickness is formed by epitaxial-growingp-type silicon with an impurity concentration of about 1×10¹⁵ cm⁻³ onthe p-type silicon substrate 11. The substrate 11 constitutes an entirepart of the first base layer and a part of the second base layer, andthe epitaxial layer 31 constitutes a part of the second base layer. Thephoto diode 111 is formed on the right side of the element formingregion, and the light signal detecting MOS transistor 112 is formed onthe left side in the neighborhood of the photo diode 111.

The n-type well layer (one conductivity type) 12 with a peak position ofabout 0.55 μm and a peak impurity concentration of about 3×10¹⁶ cm⁻³ isformed on the surface layer of the epitaxial layer 31. The n-type welllayer 12 constitutes a part of the first semiconductor layer and all thethird semiconductor layer.

The n-type buried layer (first buried layer) 32 whose peak position isabout 1.5 μm and whose peak impurity concentration is about 1×10¹⁷ cm⁻³is formed in the photo diode 111 portion to come into contact with thesubstrate 11 and the n-type well layer 12. The p-type first well layer(second semiconductor layer) 15 a with a peak position of about 0.3 μmand a peak impurity concentration of about 6×10¹⁶ cm⁻³ and with anotherpeak position of about 0.55 μm and another peak impurity concentrationof about 2×10¹⁶ cm⁻³ is formed in the overlying n-type well layer 12 tohave the substantially same width as the n-type buried layer 32. Boththe n-type buried layer (first buried layer) 32 and the first well layer15 a are formed by the ion implantation via the first mask. In thiscase, the n-type buried layer 32 constitutes a part of the firstsemiconductor layer.

Also, as shown in FIG. 6, the p-type buried layer (second buried layer)33 with a peak position of about 1.2 μm and a peak impurityconcentration of about 5×10¹⁶ cm⁻³ is formed in the light signaldetecting MOS transistor 112 portion to comes into contact with then-type well layer 12. The second well region 15 b with a peak positionof about 0.1 μm and a peak impurity concentration of about 1.2×10¹⁷ cm⁻³is formed in the overlying n-type well layer 12. Both the p-type buriedlayer (second buried layer) 33 and the second well region 15 b areformed by the ion implantation via the second mask. In this case, thep-type buried layer 33 constitutes a part of the second semiconductorlayer.

The n-type channel doped layer 15 c with a surface concentration ofabout 2×10¹⁷ cm⁻³ is formed on the surface layer of the second wellregion 15 b to touch with the high concentration buried layer 25.

Also, as shown in FIG. 6, the p⁺-type high concentration buried layer 25with a peak position of about 0.2 μm and a peak impurity concentrationof about 1×10¹⁷ cm⁻³ is formed in the second well region 15 b under thechannel doped layer 15 c. The high concentration buried layer 25 isformed by the ion implantation via the third mask.

Under this condition, as shown in FIG. 16B, first the n-type impurity ision-implanted via the gate insulating film 18 by using the gateelectrode 19 as a mask in order to form the low concentration drainstructure. Therefore, low concentration source/drain regions 116 a and117 a are formed on both sides of the gate electrode 19.

Then, as shown in FIG. 16C, the insulating film is formed by the CVD(Chemical Vapor Deposition) method, etc. Then, the sidewalls made of theinsulating film are formed on side surfaces of the gate electrode 19 bythe anisotropic etching.

Then, as shown in FIG. 16D, the resist mask 35 for covering the lightreceiving portion of the photo diode 111 is formed. After this, then-type impurity is ion-implanted by using the gate electrode 19, thesidewalls 34, and the resist mask 35 as a mask. Therefore, the highconcentration source region 116 b and the drain region 117 b as thecontact layers are formed in the center portion of the source region 116a and the peripheral portion of the drain region 117 a. At this time,the n-type high concentration source/drain regions are formedsimultaneously on both sides of the gate electrode of the n-CMOS in theperipheral circuit shown in FIG. 16F and on the outside of the n-typelow concentration source/drain regions thereof.

Then, as shown in FIG. 16E, after the resist mask 35 is removed, aninterlayer insulating film of a first layer (not shown) is formed. Inturn, the underlying source/drain electrodes or wiring layers connectedto the source/drain regions 116 b and 117 in the MOS forming region, andthe gate wiring layer 21 connected to the gate electrode 19 are formedon the interlayer insulating film of the first layer.

In turn, after an interlayer insulating film of a second layer (notshown) is formed, overlying source/drain electrodes or wiring layers 20connected to the underlying source/drain electrodes or the wiring layers22 in the MOS forming region are formed on the interlayer insulatingfilm of the second layer.

Then, after an interlayer insulating film of a third layer (not shown)is formed, the light shielding film 23 that has the opening portion(light receiving window) 24 in the photo diode 111 portion is formed onthe interlayer insulating film of the third layer. After this, the coverinsulating film (not shown) is formed to cover the overall surface ofthe device, whereby the solid state imaging device is completed.

As described above, according to the second embodiment of the presentinvention, since the unit pixel 101 consists of the photo diode 111 andthe MOS transistor 112, the pixel portion can be fabricated by using theCMOS technology. Therefore, all the above pixel portion and theperipheral circuits such as the drive scanning circuits 102 to 104, theconstant current source 106, etc. are fabricated on the samesemiconductor substrate.

As a result, simplification of the manufacturing steps can be achievedand also size reduction of the solid state imaging device can beachieved by the integration of the circuit parts. The video camera, thedigital still camera, the image input camera, the scanner, thefacsimile, or the like may be listed.

Next, another solid state imaging device according to the secondembodiment of the present invention will be explained hereunder. FIG. 17is a sectional view showing another solid state imaging device accordingto the second embodiment of the present invention. In FIG. 17, elementsindicated by the same reference symbols as those in FIG. 12 denote thesame elements as those in FIG. 12, and its explanation will be omitted.

In the structure of another solid state imaging device according to thesecond embodiment, differences from FIG. 12 are that, as shown in FIG.17, the p-type epitaxial layer 31 is not formed on the p-type substrate11, but the n-type epitaxial layer 12 which is equivalent to oneconductivity type region 12 in FIG. 12 is formed. In addition, the firstwell region 15 a and the second well region 15 b are formed in then-type epitaxial layer 12. Further, in FIG. 17, the n-type buried layer32 and the p-type buried layer 33, which are formed in the p-typeepitaxial layer 31 in FIG. 12, are not provided.

In this solid state imaging device, the impurity region 117 of the photodiode 111 and the low concentration drain region 117 a of the lightsignal detecting MOS transistor 112 are formed integrally, so that theimpurity region 117 has the impurity concentration substantiallyidentical to that of the low concentration drain region 117 a. As aresult, since the impurity region 117 can be formed at the shallowposition from the surface, the blue-color sensitivity can be improved,like the advantages in the case in FIG. 12.

As described above, the present invention is explained in detail withreference to the second embodiment. However, the scope of the presentinvention is not limited to the examples that are described concretelyin the above second embodiment, and thus modifications of the aboveembodiments may be included in the scope of the present inventionwithout departing the gist of the present invention.

For example, as shown in FIG. 15 and FIG. 6, the thickness of theepitaxial layer 31 is set to about 3 μm in the above explanation, butsuch thickness is not limited to this and may be varied appropriately toget the necessary characteristics.

Also, the peak position of the impurity concentration of the impurityregions 17, 117 and the impurity concentration at the peak position mayalso be varied appropriately to optimize the blue sensitivity accordingto the change in design of the thickness and the impurity concentrationof the epitaxial layer 31 and the other regions and layers.

In addition, the first well region 15 a and the second well region 15 bhaving a different depth are formed separately. But they may be formedtogether at once to have the same depth.

Further, the p-type substrate 11 is employed, but the n-type substratemay be used in place of this. In this case, the carriers accumulated inthe carrier pocket 25 are electrons out of the electron and the hole.Therefore, in order to achieve the similar advantages to the aboveembodiments, all conductivities of respective layers and respectiveregions explained in the above embodiments, etc. should be inverted.

Moreover, the order of steps of the solid state imaging devicemanufacturing method described in the above embodiments is a mererepresentative example. The order of steps of the manufacturing methoddescribed in the above embodiments may also be varied appropriatelywithin the range in which the device structure equivalent to the desireddevice structure obtained by the above manufacturing method can beformed.

As described above, according to the present invention, the insulatedgate field effect transistor (MOS transistor) for light signal detectionhas the low concentration drain region, and such low concentration drainregion is extended to form the impurity region of the light receivingdiode portion. In other words, the impurity region of the lightreceiving diode portion is formed integrally with the low concentrationdrain region, and thus the impurity concentration of the impurity regionis reduced.

Therefore, since the depth of the impurity region can be formed muchmore shallowly, even the blue light that has a short wavelength and isattenuated abruptly near the surface can be received at sufficientstrength.

In addition, since the light receiving diode 111 has the buriedstructure for the light emitting charge, the noise and the dark currentgenerated by the charges except the light emitting charge can bemaintained low.

As a result, the improvement of the blue sensitivity can be achievedwhile keeping the noise and the dark current low.

Furthermore, the CMOS circuit for driving the solid state imaging deviceis formed on the same substrate as the solid state imaging device, andthe low concentration impurity region 17, 117 is formed simultaneouslywhen the low concentration drain region of the MOS transistor thatconstitutes the CMOS circuit and has the LDD structure is formed, andalso the high concentration contact layer is formed simultaneously whenthe high concentration drain region of the same MOS transistor havingthe LDD structure is formed.

Accordingly, improvement of the blue sensitivity can be attained whilemaintaining the noise and the dark current without newly increasing themanufacturing steps.

What is claimed is:
 1. A solid state imaging device comprising: a photodiode formed in a second semiconductor layer of opposite conductivitytype in a first semiconductor layer of one conductivity type; and alight signal detecting insulated gate field effect transistor formed ina fourth semiconductor layer of opposite conductivity type in a thirdsemiconductor layer of one conductivity type adjacent to the photodiode; wherein a portion of the photo diode comprises an impurity regionof one conductivity type on a surface of the second semiconductor layer,and a portion of the insulated gate field effect transistor comprises asource region and a drain region of one conductivity type on a surfaceof the fourth semiconductor layer, a channel region between the sourceregion and the drain region, a gate electrode over the channel regionvia a gate insulating film, and a high concentration buried layer ofopposite conductivity type in the fourth semiconductor layer proximateto the source region under the channel region, and wherein the firstsemiconductor layer is connected to the third semiconductor layer, andthe second semiconductor layer is connected to the fourth semiconductorlayer, a portion of the insulated gate field effect transistor has a lowconcentration drain (LDD) region, and the low concentration drain regionis extended to form the impurity region that has impurity concentrationsubstantially identical to the low concentration drain region.
 2. Asolid state imaging device according to claim 1, wherein the firstsemiconductor layer is formed on a first base layer of oppositeconductivity type, and the third semiconductor layer is formed on asecond base layer of opposite conductivity type that is connected to thefirst base layer.
 3. A solid state imaging device according to claim 2,wherein the first base layer is formed of a substrate made of asemiconductor of opposite conductivity type, and the first semiconductorlayer consists of a fifth semiconductor layer containing a oneconductivity type buried layer and a one conductivity type well regionon the fifth semiconductor layer, and the second base layer consists ofa substrate made of a semiconductor of opposite conductivity type and asixth semiconductor layer containing an opposite conductivity typeburied layer on the substrate, and the third semiconductor layer isformed of the one conductivity type well region.
 4. A solid stateimaging device according to claim 1, wherein the high concentrationburied layer is formed as a partial region on a source region side in achannel length direction extended from the drain region to the sourceregion.
 5. A solid state imaging device according to claim 1, whereinthe high concentration buried layer extends in a channel widthdirection.
 6. A solid state imaging device according to claim 1, whereinthe gate electrode of the insulated gate field effect transistor has aring-like shape, the source region is formed on a surface of the fourthsemiconductor layer and is surrounded by the gate electrode, and thedrain region is formed on a surface of the fourth semiconductor layersurrounding the gate electrode.
 7. A solid state imaging deviceaccording to claim 1, wherein the gate electrode and its peripheralregion of the insulated gate field effect transistor are light-shielded.8. A solid state imaging device according to claim 1, wherein a loadcircuit is connected to the source region of the insulated gate fieldeffect transistor to form a source follower circuit.
 9. A solid stateimaging device according to claim 8, wherein a source output of thesource follower circuit is connected to a video signal output terminal.